Predictive capacitance layout method for integrated circuits

Details Predictive capacitance layout method for integrated circuits Predictive capacitance layout method for integrated circuits

1990-12-13

1994-11-22

Trans, Vincent N.

Boots, shoes, and leggings

364490, 364489, 364488, G06F 1560

Patent

active

053674693

ABSTRACT:
A method for designing a circuit layout which includes the steps of supplying a predictive capacitance value for at least one net of a circuit layout, and placing and routing all nets of the circuit layout using at least one predictive capacitance value as a layout design constraint.

REFERENCES:
patent: 4694403 (1987-09-01), Nomura
patent: 4823278 (1989-04-01), Kikuchi et al.
patent: 4924430 (1990-05-01), Zasio et al.
patent: 4947365 (1990-08-01), Masubuchi
patent: 4967367 (1990-10-01), Piednoir
patent: 5077676 (1991-12-01), Johnson et al.
patent: 5095454 (1992-03-01), Huang
"Analytical Power/Timing Optimization Technique for Digital System" by Ruehli et al., IEEE 14th Design Automation Conf., 1977, pp. 142-146.
"Circuit Placement for Predictable Performance" by Hauge et al., IEEE International Conf. on Computer Aided Design, ICCAD-87, pp. 88-91, 1987.

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