Skew adjustable IC and a method for designing the same

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Clock or pulse waveform generating

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327153, 327161, H03K 3013

Patent

active

061278742

ABSTRACT:
The present invention provides a semiconductor IC and a method for designing the same which adjusts the clock skews on a chip without additional delay circuit. A decrease in design time is realized when the semiconductor IC includes hard megacells (whose functions have been confirmed) or standard cell blocks. In the case of a semiconductor IC including hard megacells and a standard cell blocks, each megacell and standard cell block according to the present invention has sub-clock buffers on every row, for example, sub-clock buffers on the row and sub-clock buffers on the row in the megacell. The adjustment needed for accommodating clock skews on a chip is determined by calculating a delay time for the various IC chip blocks. Next, sub-clock buffers are chosen based on a result of a calculation for the delay time. Finally, the wiring design is completed which minimizes clock skew.

REFERENCES:
patent: 5012427 (1991-04-01), Kuribayashi
patent: 5077676 (1991-12-01), Johnson et al.
patent: 5548237 (1996-08-01), Iadanza et al.
patent: 5557779 (1996-09-01), Minami
patent: 5564022 (1996-10-01), Debnath et al.
patent: 5712583 (1998-01-01), Frankeny
patent: 5784600 (1998-07-01), Doreswamy et al.

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