Drain excluded EPROM cell

Static information storage and retrieval – Floating gate – Particular biasing

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Details

36518528, 257316, 257336, 257344, G11C 1300

Patent

active

056616872

ABSTRACT:
An electrically programmable floating gate memory cell is gate programmed with tunneling electrons and is not drain erasable. The memory cell comprises a semiconductor substrate, source and drain regions disposed in the semiconductor substrate, a floating gate conductor adjacent to the source and drain regions, a tunnel oxide layer disposed between the floating gate conductor and the source and drain regions, and a control gate conductor adjacent to the floating gate conductor. The source and drain regions each include a high impurity concentration portion and a low impurity concentration portion. The impurity concentration of the low impurity concentration portion is sufficiently low to prevent a substantial threshold voltage variation when a predetermined range of voltages are supplied in a first polarity between the control gate conductor and the drain region.

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