Nonvolatile semiconductor memory

Details Nonvolatile semiconductor memory Nonvolatile semiconductor memory

1995-11-08

1997-08-26

Popek, Joseph A.

Static information storage and retrieval

Floating gate

Particular biasing

36518524, 36518525, G11C 1134

Patent

active

056616864

ABSTRACT:
About 10 drive pulses, each having a predetermined positive potential of +3 V and a predetermined negative potential of -10 V, are applied to the control gate of a memory cell transistor. This drive pulse is generated in a semiconductor device on the basis of an original signal supplied from an external signal generator. By arranging the signal generator outside the semiconductor device, an increase in the necessary area of a semiconductor pellet is prevented.

REFERENCES:
patent: 4282446 (1981-08-01), McElroy
patent: 4649520 (1987-03-01), Eitan
patent: 4797856 (1989-01-01), Lee et al.
patent: 4811292 (1989-03-01), Watanabe
patent: 4931997 (1990-06-01), Mitsuishi et al.
patent: 4953123 (1990-08-01), Takeuchi et al.
patent: 4958317 (1990-09-01), Terada et al.
patent: 5068827 (1991-11-01), Yamada et al.
patent: 5075888 (1991-12-01), Yamauchi et al.
patent: 5126808 (1992-06-01), Montalvo et al.
patent: 5126969 (1992-06-01), Kawana
patent: 5132935 (1992-07-01), Ashmore, Jr.
patent: 5179536 (1993-01-01), Kasa et al.
patent: 5278794 (1994-01-01), Tanaka et al.
patent: 5282161 (1994-01-01), Villa
patent: 5283758 (1994-02-01), Nakayama et al.
patent: 5307312 (1994-04-01), Maurelli et al.
patent: 5327385 (1994-07-01), Oyama
patent: 5402373 (1995-03-01), Aritome et al.
patent: 5406521 (1995-04-01), Hara
patent: 5491656 (1996-02-01), Sawada
Patent Abstracts of Japan, vol. 16, No. 445 (P-1422), Sep. 17, 1992 & JP-A-04 155694 (Fujitsu Ltd), May 28, 1992.
International Electron Devices Meeting, Dec. 8, 1980, Washington, US, pp. 602-606, Kupec et al., "Triple level polysilicon E2PROM with single transistor per bit".
M. Lanzoni et al., "A Novel Approach to Controlled Programming of Tunnel-Based Floating-Gate MOSFET's," IEEE Journal of Solid-State Circuits, vol. 29, No. 2, Feb. 1994, pp. 147-150.
Hiroshi Gotou, "New Operation Mode for Stacked-Gate Flash Memory Cell," IEEE Electron Devices Letters, vol. 16, No. 3, Mar. 1995, pp. 121-123.

Affiliated with

Also associated with

Rating

Nonvolatile semiconductor memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Nonvolatile semiconductor memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Nonvolatile semiconductor memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1992922