Patent
1983-11-14
1984-12-18
James, Andrew J.
357 4, 357 86, H01L 2978, H01L 2712
Patent
active
044893396
ABSTRACT:
A MOS type semiconductor device effectively supplying potential to a substrate region under the channel forming region of the MOS transistor on an insulating substrate. The potential is supplied to the one conductivity type substrate region under the channel forming region which is provided on an insulating substrate and has an extended portion extending in the channel length direction, through a substrate potential take-out region of one conductivity type connecting to the extended substrate. A gate electrode with an extended gate portion is formed on the substrate region through a gate insulating film, so as to cover the substrate region.
REFERENCES:
patent: 3586930 (1971-06-01), Das et al.
patent: 3786319 (1974-01-01), Tomisaburo
patent: 4025940 (1977-05-01), Kimura et al.
patent: 4053916 (1977-10-01), Cricchi et al.
"CMOS/SOS EAROM Memory Arrays", Stewart, IEEE Journal of Solid-State Circuits, vol. SC-14, No. 5, Oct. 1979, pp. 860, 864.
James Andrew J.
Lamont John
Tokyo Shibaura Denki Kabushiki Kaisha
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