Fishing – trapping – and vermin destroying
Patent
1996-03-29
1996-12-17
Chaudhari, Chandra
Fishing, trapping, and vermin destroying
437 29, 437200, 148DIG1, H01L 21266
Patent
active
055852955
ABSTRACT:
A method for forming an inverse-T gate lightly-doped drain (ITLDD) structure for deep sub-micron metal oxide semiconductor (MOS) transistors is disclosed. The present invention includes forming a gate oxide layer on a substrate, and forming stacked-amorphous-silicon layers on the gate oxide layer, where the stacked-amorphous-silicon layers comprise at least two layers. Next, a first dielectric layer is patterned on top of the stacked-amorphous-silicon layer by a photoresist mask, and then a lightly-doped source/drain regions is formed. Thereafter, all of the stacked-amorphous-silicon layers are removed except for the bottom amorphous polysilicon layer. A second dielectric spacer is formed on the sidewalls of the stacked-amorphous-silicon layers and heavily-doped source/drain regions are formed. The bottom layer of the stacked-amorphous-silicon layers is and the gate oxide layer is removed using the spacer as an etch mask. The first dielectric layer and the second dielectric spacer is removed and a third dielectric spacer is formed on the sidewalls of the stacked-amorphous-silicon layers and the gate oxide layer. Finally, a silicide is formed on top of the stacked-amorphous-silicon layers and on portions of the heavily-doped source/drain regions.
REFERENCES:
patent: 4963504 (1990-10-01), Huang
patent: 5061647 (1991-10-01), Roth et al.
patent: 5175119 (1992-12-01), Matsutani
patent: 5304504 (1994-04-01), Wei et al.
Chaudhari Chandra
Vanguard International Semiconductor Corporation
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