Fabrication process for a 1-transistor EEPROM memory device capa

Details Fabrication process for a 1-transistor EEPROM memory device capa Fabrication process for a 1-transistor EEPROM memory device capa

1995-05-22

1996-12-17

Niebling, John

Fishing, trapping, and vermin destroying

437 44, 437 52, 257316, 257318, H01L 218247

Patent

active

055852939

ABSTRACT:
A method for fabricating a 1-transistor EEPROM device, which can be programmed and erased by Fowler-Nordheim tunneling includes the formation of a memory gate (28) overlying a tunneling region (22), and aligning source (32) and drain (34) regions in a semiconductor substrate (10), such that a vertically oriented electric field (46) is created in the tunneling region (22). The memory gate (28) is coupled to a contact region (30) by a connecting portion (31). A select gate (14) controls a portion of the channel region in the substrate (10) adjacent to the tunneling region (22). The EEPROM device is programmed by applying a voltage of a first polarity memory gate (28), while applying a voltage of a second polarity to the source region (32), the drain region (34), and to the substrate (10). Under the applied voltages, charge carriers tunnel through a tunnel oxide layer (40) and into a silicon nitride layer (42), located intermediate to the memory gate (28) and the tunnel region (22). To erase the EEPROM device, the polarity of the applied voltages is reversed, and charge carriers of an opposite conductivity type tunnel into the silicon nitride layer (42).

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