Junction field effect transistor

Details Junction field effect transistor Junction field effect transistor

1977-12-01

1979-09-25

Wojciechowicz, Edward J.

357 89, 357 90, H01L29880

Patent

active

041692691

ABSTRACT:
A junction field effect transistor has a first conductivity type substrate with high impurity concentration, a first conductivity type layer with low impurity concentration which is layered on the substrate, a first region of first conductivity type and with high impurity concentration which is formed in the surface region of the layer, and a second region of second conductivity type and with high impurity concentration which is formed in the surface region of the layer, substantially surrounding the side wall of the first region. The thickness of the layer is within the range from 4.0 to 6.0 .mu.m. The minimum width of the portion surrounded by the second region and the impurity concentration of the layer fall within the area with four corners A, B, C and D where these corners correspond to the four coordinates (log.sub.10 4.times.10.sup.15, 2.0), (log.sub.10 18.times.10.sup.15, 1.2), (log.sub.10 18.times.10.sup.15, 0.5) and (log.sub.10 4.times.10.sup.15, 1.1) of a rectangular coordinates of which the Y-distance represents the minimum width and the X-distance is the impurity concentration in the logarithmic scale.

REFERENCES:
patent: 4041517 (1977-08-01), Fuse et al.
Ozawa, Osamu, Supplement of Jap. Jour. of Applied Physics, vol. 15, 1976, pp. 171-177.

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