Method for implementing grid-based crosscheck test structures an

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437 7, 437 8, 437 57, 437 48, 324158R, 324158F, H01L 2170, H01L 2700

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050377710

ABSTRACT:
Methods for fashioning CrossCheck testing structures allow the testing of high density integrated circuit structures to be made in a space efficient manner. In one method, sense lines and probe lines are disposed in different layers perpendicular to one another and a diffusion line is overlaid in such a manner as to form a sense transistor. In another method, a pair of probe lines are routed between each pair of cells in a manner to form a sense transistor. In still another embodiment circuit layout requires no modification to the basic macrocell structure and a metal interconnection layer is used to couple sense transistors to individual cells.

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Y. Suehiro et al., "A 120K-Gate Usable CMOS Sea of Gates Packing 1.3M Transistors", Proceedings of the IEEE 1988 Custom Integrated Circuits Conference, pp. 20.5.1-20.5.4.
K. Sawada, "A 72K CMOS Channelless Gate Array with Embedded 1Mbit Dynamic RAM", Proceedings of the IEEE 1988 Custom Integrated Circuits Conference, pp. 20.3.1-20.3.4.

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