Single reference plane plastic ball grid array package

Details Single reference plane plastic ball grid array package Single reference plane plastic ball grid array package

1999-06-24

2000-10-03

Guay, John

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

257702, 257737, 257738, 257774, 257782, 361760, 361762, 361764, H01L 2312

Patent

active

061277282

ABSTRACT:
A semiconductor package is disclosed. According to one embodiment, the package comprises a substrate having a top surface with traces thereon and a bottom surface with solder balls thereon, the substrate comprising at least three material layers defining at least four substantially planar metal layers, wherein one of the metal layers comprises a reference layer that serves as a reference to both traces on a metal layer above the reference layer and traces on a metal layer below the reference layer. A semiconductor die is mounted to the substrate and bonding wires electrically connect the semiconductor die to the traces on the top surface of the substrate. The traces on the top surface of the substrate are electrically connect to the solder balls through vias and possibly through routing on another metal layer.

REFERENCES:
patent: 4965594 (1990-10-01), Komuro
patent: 5036163 (1991-07-01), Spielberger et al.
patent: 5303119 (1994-04-01), Hilbrink
patent: 5468999 (1995-11-01), Lin et al.
patent: 5500555 (1996-03-01), Ley
patent: 5808873 (1998-09-01), Celaya et al.
patent: 5886406 (1999-03-01), Bhansali
patent: 6064113 (2000-05-01), Kirkman

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