Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Patent
1998-09-03
2000-10-03
Hardy, David
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
257500, 257501, 257512, 257517, 438207, 438218, 438219, H01L 2900, H01L 218238
Patent
active
061277185
ABSTRACT:
The semiconductor device and method of manufacturing the same according to the present invention has an object of reducing hem-pulling at a side wall of an isolation trench caused at an open space of a device isolation region having a well boundary at its bottom portion thereby to prevent structurally occurrence of punch-through. In an insulator filled device isolation method, an isolation trench for device isolation is formed by dry etching. If a second isolation trench intersects an intermediate portion of a first isolation like a T-shape, one side of the first isolation trench has an open space. In this case, the inclination angle of the side wall of the first isolation trench, opposed to the open space, is loosened and the side wall forms a shape whose hem is pulled out on the bottom portion. In this case if a well boundary exists along the lengthwise direction at the bottom of the first isolation trench, the structure tends to cause punch-through easily. The present invention is characterized in that the second isolation trench intersecting the first isolation trench is inclined to reduce effectively the open space and to construct a structure in which hem-pulling of the side wall is reduced.
Ohtani Hiroshi
Okayama Yasunori
Fenty Jesse A
Hardy David
Kabushiki Kaisha Toshiba
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