Microcomputer with logic for selectively disabling serial commun

Details Microcomputer with logic for selectively disabling serial commun Microcomputer with logic for selectively disabling serial commun

1978-09-05

1982-11-30

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 300, G06F 1300, G06F 700

Patent

active

043618766

ABSTRACT:
A single-chip microcomputer includes a CPU (1), a RAM (2), a ROM (3), a timer (4), serial I/O communication logic (5), and four I/O ports (11-14). The serial I/O communication logic includes a control and status register (46), one bit (WU) of which may be utilized, when the microcomputer is connected in a distributed processing system having a shared serial communication line, to indicate that the CPU wishes to ignore a message not of interest to it. When the serial communication line again becomes free, the WU control bit is reset, enabling the CPU to intercept a new message of interest.

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Barnes et al., "Bypass Function for Stations on a Closed Communication Loop" in IBM Tech. Discl. Bull., vol. 14, No. 2, Jul. 1971, p. 488.
Thorpe, "Modular Wiring System" in IBM Tech. Discl. Bull., vol. 18, No. 10, Mar. 1976, pp. 3286-3287.

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