Pipelined arrangement including data processing storages having

Details Pipelined arrangement including data processing storages having Pipelined arrangement including data processing storages having

1994-07-05

1996-11-26

Geckil, Mehmet B.

Boots, shoes, and leggings

395591, 364DIG1, 3642318, 3642412, 3642818, G06F 1300

Patent

active

055795250

ABSTRACT:
A pipelined data processing arrangement which is subject to an instruction interrupt is disclosed. The pipelined arrangement is provided with a plurality of stages each of which has a temporary storage. In order to increase an actual time for executing instructions in the pipelined arrangement, the temporary storages which exhibit large delay are replaced by dynamic latches each having a smaller delay time without adversely affecting the operation of the pipelined arrangement.

REFERENCES:
"Modular Technique for Constructing Control Logic of a Pipelined Processor", IBM Technical Disclosure Bullentin, vol. 32, No. 7, Dec. 1989, pp. 403-425.
Hoe et al., "Pipelining of Gaas Dynamic Logic Circuits", 1992 IEEE International Symposium on Circuits and Systems, May 1992, pp. 208-211.
Patent Abstracts of Japan, vol. 7, No. 125 & JP-A-58 043 042, May 1993, Mar. 1983.

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