Integrated data processing system including CPU core and paralle

Details Integrated data processing system including CPU core and paralle Integrated data processing system including CPU core and paralle

1995-12-01

1997-02-25

An, Meng-Ai T.

Boots, shoes, and leggings

395856, 3642329, 3642379, 3642328, 364243, 364254, 3642602, 364DIG1, G06F 1300

Patent

active

056067143

ABSTRACT:
An integrated circuit structure, having a central processing unit (CPU) formed as a part thereof, for configuring the CPU for operating in an operating mode selected from a plurality of possible operating modes. The possible operating modes include a first possible operating mode that operates exclusively on internal memory storage elements, a second possible operating mode that operates exclusively on external memory storage elements via an external bus connected to a first portion of a plurality of general purpose I/O pins, and a third possible operating mode that operates on external memory storage elements via an external bus connected to a second portion of the general purpose I/O pins such that additional external I/O circuitry is necessary to handle I/O transfers.

REFERENCES:
patent: 3631405 (1969-11-01), Hoff et al.
patent: 3858182 (1974-12-01), Delagi et al.
patent: 4077038 (1978-02-01), Heller et al.
patent: 4594651 (1986-06-01), Jaswa et al.
patent: 4628448 (1986-12-01), Murao
patent: 4799144 (1989-01-01), Parruck et al.
patent: 4811345 (1989-03-01), Johnson
patent: 4860191 (1989-08-01), Nomura et al.
patent: 4968900 (1990-11-01), Harvey et al.
patent: 4991169 (1991-02-01), Davis et al.
patent: 5029204 (1991-07-01), Shenoi et al.
patent: 5086407 (1992-02-01), McGarity et al.
patent: 5113093 (1992-05-01), Tashiro et al.
patent: 5200981 (1993-04-01), Carmon
patent: 5208832 (1993-05-01), Greiss
patent: 5245632 (1993-09-01), Greiss et al.
patent: 5291614 (1994-03-01), Baker et al.
patent: 5293586 (1994-03-01), Yamazaki et al.
patent: 5355466 (1994-10-01), Iwamoto
patent: 5404547 (1995-04-01), Diamantstein et al.
patent: 5517661 (1996-05-01), Yokouchi
Ruby B. Lee; "HP Precision: A Spectrum Architecture"; Hewlett Packard Co. IEEE 1989, pp. 242-251.
Fotland, David; "Hardware Design of the First HP Precision Architecture Computers", Hewlett Packard Journal; Mar. 1987, pp. 4-17.
Ohad Falik et al; "NSC's Digital Answering Machines Solution"; IEEE 1992, pp. 132-137.
Hanoch. C. et al; "Functional Design Verification of the NS32FX16"; May 3, 1991 IEEE.
"A pipelined interfacer for high floating-point performance with precise exceptions"; IEEE Jun. 1988, pp. 77-87; Sorin Iocabovici.
"Application Specific Microprocessor"; IEEE 1990, pp. 351-354, Intrater et al.
"Architecture Considerations for SF-core Based Microprocessor"; IEEE 1991 pp. 21-23, Shacham et al.
"High performance fax processor", by National Semiconductor NSFX 16-15/NS 32 FX 16; pp. 1-84: 1990.
Sorin Iacobovici, "A Pipelined Interface for High Floating-Point Performance with Precise Exceptions," IEEE Jun. 1988, pp. 77-87.
G. Intrater et al., "Application Specific Microprocessors," IEEE 1990, pp. 351-354.
A. Shacham et al., "Architectural Considerations for SF-Core Based Microprocessor," IEEE 1991, pp. 21-23.
"High Performance Tax Processor," by National Semiconductor FSFX 16-15/NS, 32 FX 16, pp. 1-84 (1990).

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