Method and apparatus for dynamic cache memory allocation via sin

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

395463, 395440, 395449, G06F 1208

Patent

active

056066880

ABSTRACT:
A cache having dynamic cache memory allocation is provided. A cache memory stores a plurality of data blocks, each block belonging to one of a plurality of data sets. A cache directory maintains a list of entries associated with the data blocks stored in the cache memory, wherein each entry corresponds to an individual data block and has fields for storing information including a designation of the data set to which the corresponding data block belongs. A directory controller generates each entry when the corresponding data block is loaded in the cache. The directory controller inserts the generated entry into the list at the optimal insertion point for the data block's data set, which is derived from a calculated optimal single-reference residency time for that data set. Further, the directory controller moves an entry in the list to the insertion point for the given data set of a corresponding data block when the corresponding data block is referenced in the cache. A storage control unit for storing data blocks within the cache memory replaces in the cache memory the data block corresponding to the bottom entry of the list with the data block corresponding to an entry inserted into the list.

REFERENCES:
patent: 4008460 (1977-02-01), Bryant et al.
patent: 4168541 (1979-09-01), DeKarske
patent: 4322795 (1982-03-01), Lange et al.
patent: 4334289 (1982-06-01), Lange et al.
patent: 4437155 (1984-03-01), Sawyer et al.
patent: 4463420 (1984-07-01), Fletcher
patent: 4463424 (1984-07-01), Mattson et al.
patent: 4464712 (1984-08-01), Fletcher
patent: 4489378 (1984-12-01), Dixon et al.
patent: 4490782 (1984-12-01), Dixon et al.
patent: 4507729 (1985-03-01), Takahashi et al.
patent: 4530054 (1985-07-01), Hamstra et al.
patent: 4695943 (1987-09-01), Keeley et al.
patent: 4783735 (1988-11-01), Miu et al.
patent: 4785395 (1988-11-01), Keeley
patent: 4802086 (1989-01-01), Gay et al.
patent: 4811203 (1989-03-01), Hamstra
patent: 4835686 (1989-05-01), Furuya et al.
patent: 4905139 (1990-02-01), Asai et al.
patent: 4920478 (1990-04-01), Furuya et al.
patent: 4951194 (1990-08-01), Bradley et al.
patent: 4956803 (1990-09-01), Tayler et al.
patent: 5043885 (1991-08-01), Robinson
patent: 5113510 (1992-05-01), Hillis
patent: 5140690 (1992-08-01), Hata et al.
patent: 5150472 (1992-09-01), Blank et al.
patent: 5297265 (1994-03-01), Frank et al.
patent: 5390318 (1995-02-01), Ramakrishnan et al.
patent: 5434992 (1995-07-01), Mattson
patent: 5457793 (1995-10-01), Elko et al.
Arnold, R. F., et al., Adaptive Time Stamp Mechanism, IBM Technical Disclosure Bulletin, 12-73, Dec., 1973, pp. 2209-2213.
Weiner, A. M., Biased Partitioned LRU Cache Replacement Control, IBM Technical Disclosure Bulletin, vol.05-77, May, 1977, p. 4697.
Kamionka, H. E., et al., Limited Replacement and Migration Controls, IBM Technical Disclosure Bulletin, vol. 08-83, Aug., 1983, pp. 1746-1747.
Liu, L., Upgrading LRU Positions in Cache Management, IBM Technical Disclosure Bulletin, vol. 10-87, Oct., 1987, pp. 358-359.
Stone, H. S., et al., Means For Achieving Optimum of Cache Among Data And . . . , IBM Technical Disclosure Bulletin, No. 8A, 01-90, Jan., 1990, pp. 381-383.
Stone, H. S., Means For Improving the Performance of Multiprogrammed Cache, IBM Technical Disclosure Bulletin, No. 4, 09-90, Sep., 1990, pp. 3-5.
Dan, A., et al., Use of Secondary Address Stack and Multiple Insertion Points For Database Buffer Management Under Least Recently Used Policy, IBM Technical Disclosure Bulletin, vol. 36 No. 7, 07-93, Jul., 1993, pp. 431-432.
Mano, Memory Organization, Computer System Architecture, 2nd Edition, pp. 478-482 1982.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method and apparatus for dynamic cache memory allocation via sin does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for dynamic cache memory allocation via sin, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for dynamic cache memory allocation via sin will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1980747

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.