Method and apparatus for streamlined concurrent testing of elect

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364579, 364580, 371 226, G06F 11267

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056065663

ABSTRACT:
An electrical circuit includes a serial scan test architecture having first and second separate serial scan paths respectively coupled to first and second portions of the electrical circuit for permitting data to be scanned through the electrical circuit for testing thereof. The first serial scan path is operatively enabled while the second serial scan path is also operatively enabled, thereby permitting concurrent scan testing of the first and second portions of the electrical circuit. Test signals are transferred between the first serial scan path and the first portion of the electrical circuit and between the second serial scan path and the second portion of the electrical circuit while serial test data is being transferred in first and second continuous serial data streams through the first and second serial scan paths, respectively.

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Lee Whetsel, "An IEEE 1149.1 Based Logic/Signature Analyzer in a Chip", International Test Conference, Oct. 26-30, 1991.

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