Semiconductor memory device and method of manufacturing the same

Details Semiconductor memory device and method of manufacturing the same Semiconductor memory device and method of manufacturing the same

1995-09-26

1996-11-26

Nelms, David C.

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

365236, 365200, 365178, G11C 800, G11C 700, G11C 1134

Patent

active

055792790

ABSTRACT:
A memory system having an input buffer, an address counter, an address decoder, and a memory-cell array. Address signals are supplied to the memory-cell array. In the system, a true-address data determining section has wires or a circuit storing an internal address specific to the system. A false-data generating circuit generates false data when the internal address is in a false data area, and the false data is input to an output selecting circuit. A true-address data area detecting circuit compares the true-address data EAi with the internal address consisting of the address signals supplied from an address counter, and generates a signal REAL when the internal address is in a true-address data area. The output-selecting circuit selects the false data or the data read from the memory-cell array through a sense amplifier, in accordance with whether the signal REAL is at high level or low level. The data stored in the memory-cell array consists of true data items and false data items. Hence, even if the data is copied into a conventional semiconductor memory device, it cannot be used in practice.

REFERENCES:
patent: 4346459 (1982-08-01), Sud et al.
patent: 5303201 (1994-04-01), Sakamoto

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