Parity checking scheme for detecting word line failure in multip

Details Parity checking scheme for detecting word line failure in multip Parity checking scheme for detecting word line failure in multip

1976-12-20

1978-08-01

Smith, Jerry

Registers

Systems controlled by data bearing records

Time analysis

235306, G06F 1100, G11C 2900

Patent

active

041038231

ABSTRACT:
A parity checking scheme for detecting memory array word line failures whereby all of the data and parity bits of a plurality of bytes sharing the same word line erroneously assume the value "1" or the value "0". When storing data in the array, the data and parity bits comprising each byte are stored directly except for the parity bit of a selected one of the bytes, which parity bit is inverted by a gated inverter circuit before storing. The same gated inverter circuit also inverts the parity bit of the selected byte upon reading the stored data. All of the remaining bits of all of the remaining bytes are read directly. The read bits of each byte are applied to a respective parity checking circuit of the same even or odd parity type as is used in storing the data. The outputs of all of the parity checking circuits are applied to error control logic.

REFERENCES:
patent: 3768071 (1973-10-01), Knauft et al.
patent: 4016409 (1977-04-01), Kim
patent: 4028539 (1977-06-01), Jacobs

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