Method and system for efficiently utilizing rename buffers to re

Details Method and system for efficiently utilizing rename buffers to re Method and system for efficiently utilizing rename buffers to re

1995-12-14

1998-05-26

Lim, Krisna

395395, G06F 938

Patent

active

057581177

ABSTRACT:
A method for reducing dispatch stalls includes tracking allocation and deallocation of real rename buffers for instructions dispatched by a dispatch unit, and providing at least one virtual rename buffer for allocation of an instruction when the real rename buffers have been allocated. The method further includes tagging the instruction allocated to the at least one virtual rename buffer with a rename buffer busy signal, wherein the rename buffer busy signal indicates to an execution unit that the instruction cannot be completed. An efficient system for utilization of rename buffers in a superscalar processor includes a plurality of rename buffers, a dispatch unit coupled to the plurality of rename buffers, and an allocation/deallocation table coupled to the dispatch unit and the plurality of rename buffers. Further, the table includes a plurality of real rename buffer slots and at least one virtual rename buffer slot. Additionally, a rename busy signal is provided for an instruction allocated to the at least one virtual rename buffer slot.

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IBM Technical Disclosure Bulletin, vol. 37 No. 10, Oct. 1994; pp. 143-145.

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