Interoperability with multiple instruction sets

Details Interoperability with multiple instruction sets Interoperability with multiple instruction sets

1995-06-07

1998-05-26

Harrell, Robert B.

395386, G06F 930

Patent

active

057581150

ABSTRACT:
Data processing apparatus comprising: a processor core having means for executing successive program instruction words of a predetermined plurality of instruction sets; a data memory for storing program instruction words to be executed; a program counter register for indicating the address of a next program instruction word in the data memory; means for modifying the contents of the program counter register in response to a current program instruction word; and control means, responsive to one or more predetermined indicator bits of the program counter register, for controlling the processor core to execute program instruction words of a current instruction set selected from the predetermined plurality of instruction sets and specified by the state of the one or more indicator bits of the program counter register.

REFERENCES:
patent: 5404472 (1995-04-01), Kurosawa et al.
patent: 5568646 (1996-10-01), Jagger
patent: 5574928 (1996-11-01), White et al.
patent: 5598546 (1997-01-01), Blomgren
patent: 5638525 (1997-06-01), Hammond et al.

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