Method of forming a capacitor

Fishing – trapping – and vermin destroying

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Details

437 47, 437 48, 437 52, 437919, 437981, H01L 2170

Patent

active

052081800

ABSTRACT:
A method of forming a capacitor on a semiconductor wafer includes: a) providing a layer of insulating dielectric; b) providing a mask with an aperture of a selected diameter over the dielectric for definition of a contact opening to a defined area on the wafer; c) isotropically etching the insulating dielectric through the aperture to a selected depth which is less than the dielectric thickness, thereby defining a first contact opening of a selected diameter having non-perpendicular angled ramps; d) anisotropically etching the insulating dielectric through the aperture and first contact opening to the defined area on the wafer thereby defining a second contact opening which extends to the defined area on the wafer; e) depositing a non-conformal layer of polysilicon atop the wafer which is thicker atop the dielectric layer than within the second contact opening, and is thickest over the angled ramps; f) selectively masking polysilicon within the first and second contact openings for definition of a capacitor storage node; g) anisotropically etching the masked polysilicon layer to leave polysilicon atop the non-perpendicular angled ramp portions to provide non-perpendicularly angled projecting polysilicon portions; h) providing a layer of cell dielectric atop the wafer and over polysilicon remaining in the first and second contact openings; and i) providing a layer of conductive material atop the cell dielectric layer.

REFERENCES:
patent: 4742018 (1988-03-01), Kimura et al.
patent: 4970564 (1990-11-01), Kimura et al.

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