Method for forming a raised vertical transistor

Details Method for forming a raised vertical transistor Method for forming a raised vertical transistor

1992-03-02

1993-05-04

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 89, 437915, 437913, 437 60, H01L 21265

Patent

active

052081729

ABSTRACT:
A vertical transistor (10) has a substrate (12) and a control electrode conductive layer (18), which functions as a control or gate electrode. A sidewall dielectric layer (22) is formed laterally adjacent the control electrode conductive layer (18) and overlying the substrate (12). The conductive layer (18) at least partially surrounds a channel region (30). A vertical conductive region is formed within a device opening wherein a bottom portion of the conductive region is a first current electrode (28). A middle portion of the vertical conductive region is the channel region (30). A top portion of the vertical conductive region is a second current electrode (34).

REFERENCES:
patent: 4663831 (1987-05-01), Birrittella et al.
patent: 4764801 (1988-08-01), McLaughlin et al.
patent: 4860077 (1989-08-01), Reuss et al.
patent: 4902641 (1990-02-01), Koury, Jr.
"Impact of Surrounding Gate Transistor (SGT) for Ultra-High-Density LSI's", by Hiroshi Takato et al., was published in IEEE Trans. on Electron Devices, vol. 38, No. 3, Mar. 1991, pp. 573-577.

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