Method for fabricating bipolar and CMOS devices in integrated ci

Details Method for fabricating bipolar and CMOS devices in integrated ci Method for fabricating bipolar and CMOS devices in integrated ci

1991-09-18

1993-05-04

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 31, 437183, 437189, 437200, H01L 21265

Patent

active

052081702

ABSTRACT:
A method for fabricating bipolar and CMOS devices in integrated circuits using W as a local interconnect and via landing pad for bipolar and CMOS devices. The method includes the forming of an oxide/silicon bilayer above a local interconnect of tungsten/titanium wherein the oxide is patterned as a mask for the silicon/tungsten/titanium reactive ion etch, and the silicon layer above the tungsten/titanium layer is used as an etch stop for a via etch. The silicon layer is then reacted and converted to titanium silicide after the via etch to provide a low resistance path in the via from the local interconnect in a self aligned manner.

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