Method of forming high voltage bipolar transistor for a BICMOS i

Details Method of forming high voltage bipolar transistor for a BICMOS i Method of forming high voltage bipolar transistor for a BICMOS i

1991-06-28

1993-05-04

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 75, 437 76, 437 26, 437909, 148DIG11, H01L 21265

Patent

active

052081699

ABSTRACT:
A high voltage bipolar transistor (10) is fabricated in an N- HV/epitaxial well (12) formed by an N- substrate implant and the overlying portion of the N- epitaxial layer 12b. The N- substrate implant replaces the normal buried N+ collector layer, in effect extending the depth of the epitaxial layer to increase junction breakdown voltages. The collector is formed by buried N+ collector regions (14a and 14b) formed adjacent to, and on either side of, the N- substrate implant. The transistor is fabricated conventionally in the N- HV/epitaxial well, except that, to further enhance high voltage performance, P+ extrinsic base regions (23a and 23b) can be extended using optional deep P+ implants (reducing curvature effects which correspondingly reduces electric field, and thereby inhibits premature junction breakdown).

REFERENCES:
patent: 4272307 (1981-06-01), Mayrand
patent: 4525922 (1985-07-01), Kiriseko
patent: 4879255 (1989-11-01), Deguchi et al.
patent: 4997775 (1991-03-01), Cook et al.
patent: 5116777 (1992-05-01), Chan et al.

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