Fishing – trapping – and vermin destroying
Patent
1995-05-05
1997-02-25
Chaudhari, Chandra
Fishing, trapping, and vermin destroying
437 34, H01L 21225
Patent
active
056058616
ABSTRACT:
A method of forming a CMOS transistor which comprises providing a partially fabricated CMOS structure having a p-type region wherein NMOS devices will be fabricated and an n-type region wherein PMOS devices will be fabricated, a separate pattern defining each region, a thin gate oxide layer in each window and a thin polysilicon gate layer having a thickness up to 3200 .ANG. over the thin gate oxide layer having a thickness up to 90 .ANG.. A layer of glass having a boron doping species therein, preferably borosilicate glass, is deposited over the polysilicon gate layer disposed over the the n-type region. The portion of the polysilicon gate layer disposed defining the p-type region is then doped n-type, preferably by implanting phosphorus, and the structure is heated to cause boron to diffuse from the layer of glass into the polysilicon gate layer over the n-type region. The layer of glass of glass is removed and fabrication of the CMOS device is then completed in standard manner.
REFERENCES:
patent: 4345366 (1982-08-01), Brower
patent: 4599789 (1986-07-01), Gasner
patent: 4703552 (1987-11-01), Baldi et al.
Brady III W. James
Chaudhari Chandra
Donaldson Richard L.
Texas Instruments Incorporated
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