Method of forming a bit line over capacitor array of memory cell

Details Method of forming a bit line over capacitor array of memory cell Method of forming a bit line over capacitor array of memory cell

1995-02-22

1997-02-25

Chaudhari, Chandra

Fishing, trapping, and vermin destroying

437228, 148DIG50, H01L 218242

Patent

active

056058578

ABSTRACT:
A semiconductor memory device includes, a) a semiconductor substrate; b) a field effect transistor gate positioned outwardly of the semiconductor substrate; c) opposing active areas formed within the semiconductor substrate on opposing sides of the gate; d) a capacitor electrically connected with one of the active areas; the capacitor comprising an inner storage node, a capacitor dielectric layer, and an outer cell node; the inner storage node electrically connecting with the one active area, the inner storage node having an upper surface at an elevation; e) a bit line; f) a dielectric insulating layer positioned intermediate the bit line and the other active area; and g) an electrically conductive bit line plug extending through the insulating layer to contact with the other active area and electrically interconnect the bit line with the other active area, the bit line plug being homogeneous in composition between the other active area and the elevation of the inner storage node upper surface. A method of producing such a construction is also disclosed.

REFERENCES:
patent: 5030587 (1991-07-01), Wald et al.
patent: 5227322 (1993-07-01), Ko et al.
patent: 5459105 (1995-10-01), Matsuura
patent: 5488007 (1996-01-01), Kim et al.

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