MOS array multiplier cell

Details MOS array multiplier cell MOS array multiplier cell

1991-10-02

1992-09-29

Mai, Tan V.

Boots, shoes, and leggings

364758, G06F 750, G06F 752

Patent

active

051518759

ABSTRACT:
A complementary metal-oxide semiconductor (CMOS) array multiplier cell comprising two CMOS equivalence circuits for sum generation, two pass transistors and an inverter for carry generation, and a multiplier selector built of a matrix of identical selection elements, a single field effect transistor (FET) switch and an inverter. Each of the selection elements consists of an N-channel FET, a P-channel FET and an inverter. Each equivalence circuit utilizes six transistors: four FET's and an inverter. Total cell device count is 31 to 39 transistors, depending on implementation alternatives.

REFERENCES:
patent: 4363107 (1982-12-01), Ohhashi et al.
patent: 4369500 (1983-01-01), Fette
patent: 4575812 (1986-03-01), Kloker et al.
patent: 4752905 (1988-06-01), Nakagawa et al.
patent: 4831578 (1989-05-01), Bui
patent: 4901270 (1990-02-01), Galbi et al.
patent: 4916336 (1990-04-01), Houston

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