Method for forming inlaid interconnects in a semiconductor devic

Details Method for forming inlaid interconnects in a semiconductor devic Method for forming inlaid interconnects in a semiconductor devic

Filed on

1995-05-18

Date issued

1996-11-26

Examiner

Nguyen, Tuan H.

Patent Class

Fishing, trapping, and vermin destroying

Other Related Categories

437192, 437194, 437195, 437228, 437203, H01L 2144

Type

Patent

Status

active

Patent number

055785239

Description

ABSTRACT:
In the present invention, an inlaid interconnect (44) is formed by chemical mechanical polishing. A polish assisting layer (31), in the form of an aluminum nitride layer, is formed between an interlayer dielectric (30) and an interconnect metal (42) to prevent dishing or cusping of the interconnect upon polishing. By allowing the sacrificial polish assisting layer (31) to be removed at close to the same rate as interconnect metal (42) during the final stages of polishing, dishing is avoided. The aluminum nitride layer also facilitates chemical vapor deposition of aluminum as the interconnect metal by providing a more suitable nucleation site for aluminum than exists with silicon dioxide.

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