Patent
1990-11-20
1992-09-29
Jackson, Jr., Jerome
357 59, H01L 2348, H01L 2946, H01L 2954, H01L 2904
Patent
active
051517728
ABSTRACT:
A semiconductor integrated circuit device is provided which includes a memory cell array located in a generally central area of a semiconductor substrate with peripheral circuits located at both ends of the semiconductor substrate. A wiring layer is also provided which couples the peripheral circuits to one another. This wiring layer is arranged to have a double-layer structure of first and second aluminum layers which are electrically coupled to one another.
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Ishihara Masamichi
Iwai Hidetoshi
Kimura Katsutaka
Koyama Yoshihisa
Matsuura Hiromi
Hitachi , Ltd.
Hitachi VLSI Engineering Corp.
Jackson, Jr. Jerome
Monin D.
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