Method and apparatus for scan out testing of integrated circuits

Details Method and apparatus for scan out testing of integrated circuits Method and apparatus for scan out testing of integrated circuits

1996-11-26

1998-05-26

Nguyen, Hoa T.

Excavating

371 2232, 371 2234, G01R 3128

Patent

active

057578184

ABSTRACT:
An apparatus for sampling logic states of a plurality of nodes of an integrated circuit. A selector circuit is coupled to the plurality of nodes of the integrated circuit and to a scan cell. The selector circuit comprises a plurality of control inputs, wherein each combination of logic states of the plurality of control inputs causes the selector circuit to output to the scan cell a logic value of a particular one of the nodes of the integrated circuit.

REFERENCES:
patent: 5253255 (1993-10-01), Carbine
patent: 5448166 (1995-09-01), Parker et al.
patent: 5465053 (1995-11-01), Edwards
patent: 5488731 (1996-01-01), Mendelsohn
patent: 5583787 (1996-12-01), Underwood et al.

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