Memory device having erasable frohmann-bentchkowsky EPROM cells

Details Memory device having erasable frohmann-bentchkowsky EPROM cells Memory device having erasable frohmann-bentchkowsky EPROM cells

1999-04-28

2000-10-24

Nelms, David

Static information storage and retrieval

Floating gate

Particular biasing

36518505, 36518529, 36518528, G11C 1604

Patent

active

06137721&

ABSTRACT:
A memory device is disclosed which includes a plurality of memory cells formed in rows and columns. Each memory cell includes an erasable Frohmann-Bentchkowsky p-channel memory transistor and an n-channel MOS access transistor. The memory device utilizes a plurality of erase lines which are formed adjacent to the floating gates of the memory transistors to provide electrical erasability.

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D. Frohmann-Bentchkowsky, "A Fully Decoded 2048-bit Electrically-Programmable MOS-ROM," 1971 IEEE International Solid-State Circuits Conference, Feb. 18, 1971, ISSCC Digest of Technical papers, pp. 80-81; p. 200, Univ. of Pennsylvania.

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