Video signal multiplying circuit

Details Video signal multiplying circuit Video signal multiplying circuit

1983-03-03

1985-04-30

Martin, John C.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

358184, 358221, H04N 514, H04N 534

Patent

active

045147620

ABSTRACT:
A video signal multiplying circuit with automatic correction of a time-varying unbalance at a signal multiplier (1). A combination of a multiplying signal (MS) and a periodically pulse-shaped signal (HS) having a pulse in a blanking period (THB) is applied to the signal multiplier (1). An output (4) of the signal multiplier (1) is fedback via a signal sample-and-hold circuit (20, 21, 24, 25) and a subsequent signal comparison-and-integrating circuit (16, 17, 18) to an input (2) of the multiplier (1) to which also a video signal (VS) is applied. Signal samples are taken in the blanking period (THB), more specifically during the duration of the said pulse and outside this pulse duration. The result is that the black level in the multiplied video signal (MVS) is not influenced by the unbalance.

REFERENCES:
patent: 3743772 (1973-07-01), Pieters et al.
patent: 4354200 (1982-10-01), Haenen et al.

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