Semiconductor memory device having wiring for selection of redun

Details Semiconductor memory device having wiring for selection of redun Semiconductor memory device having wiring for selection of redun

1997-06-05

1998-05-26

Le, Vu A.

Static information storage and retrieval

Interconnection arrangements

365 51, 365200, G11C 506

Patent

active

057576912

ABSTRACT:
A semiconductor memory device includes: cell arrays each including a normal cell array portion and a redundant cell array portion in which a plurality of normal cells and a plurality of redundant cells are arranged respectively; a first wiring, laid out in a row direction within the redundant cell array portions, for selecting the redundant cells; a second wiring orthogonal to the first wiring and formed on a different wiring layer from the first wiring; a peripheral circuit region; and a redundancy judgment circuit placed in the peripheral circuit region. The first wiring is connected with the second wiring within the cell arrays, and connected to the redundancy judgment circuit by way of the second wiring. Owing to this configuration, the wiring for selecting the redundant cells can be arranged without the need of forming a useless region on a chip. This contributes to the effort to stop the area of a chip from increasing.

REFERENCES:
patent: 5621679 (1997-04-01), Seo et al.
patent: 5687108 (1997-11-01), Proebsting

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