Programmable logic device with multiple, flexible asynchronous p

Details Programmable logic device with multiple, flexible asynchronous p Programmable logic device with multiple, flexible asynchronous p

1991-10-18

1992-09-29

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307480, 36518908, H03K 19177

Patent

active

051516233

ABSTRACT:
An asynchronous high density segmented programmable array logic device utilizes a programmable switch interconnection matrix to couple an array of symmetric programamble logic blocks. Each programmable logic block includes programmable output logic macrocells, programmable input/output macrocells, programmable input logic macrocells, a logic allocator and a programmable product term array. Further, the switch matrix provides centralized global routing with a fixed path independent delay. The programmable switch interconnection matrix decouples the output logic macrocells from the product term array. The logic allocator decouples the product term array from the output logic macrocells, and the I/O macrocells decouple the output logic macrocells from the package I/O pins. Thus, the architecture of this invention is easily scalable to higher density devices without compromising speed. The logic allocator steers product terms from the product term array to selected logic macrocells so that no logic product terms are permanently allocated to a specific logic macrocell. Each output logic macrocell is provided three dedicated control product terms from the programmable product term array and each I/O macrocell is provided one control product term from the programmable product term array in one embodiment. These four dedicated product terms are used to implement asynchronous applications. Each asynchronous programmable logic device of this invention is derived from the core of a programmable logic device in a family of synchronous programmable logic devices.

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