Fishing – trapping – and vermin destroying
Patent
1994-11-30
1995-11-07
Chaudhari, Chandra
Fishing, trapping, and vermin destroying
437 44, 437158, H01L 218247
Patent
active
054647851
ABSTRACT:
A MOSFET device has a floating gate and a control gate formed over a lightly P- doped semiconductor substrate with an N+ source region and an N+ drain region, includes a tunnel oxide dielectric layer on the substrate. A stack of gate layers includes a floating gate conductor overlying the first dielectric layer, an interconductor, ONO, dielectric layer over the floating gate conductor, and a control gate electrode over the interconductor dielectric layer. A P+, ion implanted, drain edge region is adjacent to the drain region in the substrate. The N+ source region and the N+ drain region are self-aligned with the stack, and an ion implanted N- region in the substrate is formed beneath the N+ source. Source/drain implant regions comprises arsenic ions implanted at between about 30 keV and about 100 keV and between about 1E15 cm.sup.-2 and about 8E15 cm.sup.-2. In manufacture a sacrificial layer is formed over the stack, then etched away from the device to form, with a mask, a deep trench adjacent to the source region and a trench adjacent the drain region between the edges of the stack and the mask.
REFERENCES:
patent: 4442589 (1984-04-01), Doo et al.
patent: 4814286 (1989-03-01), Tam
Chaudhari Chandra
Jones II Graham S.
Saile George O.
United Microelectronics Corporation
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