Input receiver circuit

Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude

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Details

327 77, 327 78, 327 81, G01R 1900

Patent

active

061373206

ABSTRACT:
An input receiver circuit which is capable of reducing a difference between a propagation time at the rise-up and that at the fall of an input signal and is suitably used for semiconductor memory devices. The input receiving circuit comprises a node, six N channel (N-ch) MOS transistors and two P channel (P-ch) MOS transistors. The first and second N-ch transistors receive an activation signal and have grounded sources. The third and fourth N-ch transistors receive the first and second signal and have sources connected to the drains of the first and second N-ch transistors, respectively. The fifth and sixth N-ch transistors have gates connected to the node and are provided in parallel to the third and fourth N-ch transistors, respectively. Sources of the first and second P-ch transistors are supplied with the power source voltage. Drains of the first and second P-ch transistors are connected to the drains of the third and fourth N-ch transistors, respectively. Gates of the first and second P-ch transistors are connected to the node. The second P-ch transistor outputs a drain voltage as an output signal.

REFERENCES:
patent: 4461964 (1984-07-01), Shiotari
patent: 5148063 (1992-09-01), Hotta
patent: 5789948 (1998-08-01), Kim et al.
patent: 5883535 (1999-03-01), Kato

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