Semiconductor memory array having shared column redundancy progr

Active solid-state devices (e.g. – transistors – solid-state diode – Contacts or leads including fusible link means or noise...

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714711, H01L 2358, H01L 2362, G11C 2900

Patent

active

061371572

ABSTRACT:
Surface area of a semiconductor integrated circuit memory required by programmable fuse boxes is reduced, and the capacitive loading of a column address bus from the programmable fuse boxes is reduced by reducing the number of programmable boxes. Each programmable fuse box is connected through fuses to a plurality of redundant columns in memory arrays whereby any one or more of the redundant column lines can be addressed through the programmed fuse box in replacing a defective column line. An unprogrammed redundant column select line is connected to ground through the fuses connecting the unselected redundant column select lines to ground so that unprogrammed redundant columns are inactive.

REFERENCES:
patent: 5610865 (1997-03-01), Shin et al.
patent: 5732029 (1998-03-01), Lee et al.
patent: 5999463 (1999-12-01), Park et al.

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