Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Patent
1998-04-22
2000-10-24
Crane, Sara
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
257506, 257513, H01L 2900
Patent
active
061371521
ABSTRACT:
The trench isolation structure in the present invention is as follows. A lower-half trench is in the substrate. An upper-half trench in the substrate is located above the lower-half trench and the upper-half trench has a larger width than the lower-half trench. A first insulating layer is right above the lower-half trench and the upper-half trench. A second insulating layer is located over the first insulating layer. A semiconductor layer is within the lower-half trench over a portion of the second insulating layer. A third insulating layer is located on the second insulating layer and the semiconductor layer and is located within the upper-half trench. The planarized deep-shallow trench isolation in the present invention can be employed for isolating CMOS and bipolar devices. A higher packing density than conventional trench isolation is provided.
REFERENCES:
patent: 4472240 (1984-09-01), Kameyama
patent: 5298450 (1994-03-01), Verret
patent: 5358891 (1994-10-01), Tsang et al.
patent: 5385861 (1995-01-01), Bashir et al.
patent: 5387540 (1995-02-01), Poon et al.
patent: 5411913 (1995-05-01), Bashir et al.
patent: 5433794 (1995-07-01), Fazan et al.
patent: 5474953 (1995-12-01), Shimizu et al.
patent: 5536675 (1996-07-01), Bohr
patent: 5576241 (1996-11-01), Sakai
patent: 5763315 (1998-06-01), Benedict et al.
A.E.T. Kuiper et al., Oxidation Behaviour of LPCVD Silicon Oxynitride Films, Applied Surface Science 33/34, 1988, pp. 757-764.
R. Bashir et al., PLATOP: A Novel Planarized Trench Isolation and Field Oxide Formation Using Poly-Silicon, IEEE Electron Device Letters, vol. 17, No. 7, Jul. 1996, pp. 352-354.
Crane Sara
Texas Instruments - Acer Incorporated
LandOfFree
Planarized deep-shallow trench isolation for CMOS/bipolar device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Planarized deep-shallow trench isolation for CMOS/bipolar device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Planarized deep-shallow trench isolation for CMOS/bipolar device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1966521