Patent
1991-01-07
1992-10-20
Hille, Rolf
357 72, H01L 2348, H01L 2330, H01L 2350
Patent
active
051574756
DESCRIPTION:
BRIEF SUMMARY
DESCRIPTION
1. Technical Field
The present invention relates to a resin-sealed, thin semiconductor device, such as an IC card.
2. Background Art
Semiconductor devices for watches, cameras and IC cards are required to be formed in a very thin package having a thickness, for example, in the range of about 0.5 to about 2 mm.
Such semiconductor devices are disclosed in Japanese Patent laid-open Nos. 55-56647 (Reference 1) and 62-261498 (Reference 2).
The semiconductor device disclosed in Reference 1 is shown in FIGS. 1(a), 1(b), 2(a) and 2(b). FIGS. 1(a) and 2(a) are plan views and FIGS. 1(b) and 2(b) are sectional views of the semiconductor device, in which like parts are denoted by the same reference characters throughout.
The semiconductor device shown in FIGS. 1(a) and 1(b) employs a printed circuit board (hereinafter abbreviated to "PCB") 1 formed of a glass cloth base epoxy resin laminate and provide with leads 1a and 1b formed of metal films in desired patterns on the opposite sides thereof, respectively. A semiconductor chip 2 mounted on the PCB 1 is connected to the leads 1a with wires 3. The semiconductor chip 2 and the wires 3 are sealed in a sealing material 4, such as an epoxy resin, to form a so-called chip-on-board (COB) semiconductor device. The leads 1b formed on the backside of the PCB 1 are connected electrically to an external device.
The semiconductor device shown in FIGS. 2(a) and 2(b) is of a two-layer stacked construction having two PCBs 1-1 and 1-2. A semiconductor chip 2 is fixedly seated in a recess 1c formed in the upper surface of the lower PCB 1-1 and sealed in a sealing material 4. The outer surface of the upper PCB 1-2 forming the upper surface of this semiconductor device is flat. The outer surface of the sealing material 4 can be formed flush with the outer surface of the upper PCB 1-2, and the semiconductor chip 2 is seated in the recess 1c so that the semiconductor device is formed in a relatively small thickness. Such a construction is suitable for a thin semiconductor device having flat surfaces, such as an IC card.
The semiconductor devices of FIGS. 1(a) and 2(a), however, employ the expensive PCB 1, and the PCBs 1-1 and 1-2, respectively, as the principle components, and the use of the two PCBs 1-1 and 1-2 as best shown in FIG. 2(b) further increases the manufacturing cost of the semiconductor device. Semiconductor devices employing lead frames as shown in FIGS. 3(a), 3(b), 4(a) and 4(b) are proposed in Reference 2.
FIGS. 3(a) and 3(b) are a plan view and a sectional view, respectively, of the semiconductor device proposed in Reference 2. This semiconductor device employs a lead frame having a die pad 10a and a plurality of leads 10b. A semiconductor chip 11 is fixed to the die pad 10a and is connected electrically with wires 12 to the leads 10b. The lead frame thus mounted with the semiconductor chip 11 is held between the upper and lower dies of a molding die, not shown, and is sealed in a sealing material 13 by molding.
FIG. 4(a) is a perspective view of a lead frame employed in a conventional semiconductor device for an IC card, and FIG. 4(b) is a perspective view of an IC card incorporating the lead frame of FIG. 4(a).
Referring to FIG. 4(a), the terminals 20a of a lead frame 20 are formed by pressing or embossing so as to protrude by a height in the range of 20 to 300 .mu.m from a plane including the upper surfaces of leads 20b. The lead frame 20 is combined with a laminated film 22 with the terminals 20a fitted in through holes formed in the laminated film 22, and then the laminated film 22 is applied to a card 21 to construct an IC card having flat surfaces as shown in FIG. 4(b).
These semiconductor devices employing the lead frames shown in FIGS. 3(a) and 4(a), however, have the following disadvantages.
(a) In sealing the semiconductor device by molding, the leads of the lead frame cannot be held between the upper and lower dies of the molding die in perfect contact with the inner surfaces of the upper and lower dies and, consequently, the sealing material inje
REFERENCES:
patent: 3964093 (1976-06-01), Coucoulas
patent: 4099200 (1978-07-01), Koutalides
patent: 4864383 (1989-09-01), Gloton et al.
Clark S. V.
Hille Rolf
Manzo Edward D.
OKI Electric Industry Co., Ltd.
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