Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1994-04-05

1996-03-19

Nguyen, Viet Q.

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

36523006, 365233, 365236, 36523001, G11C 800

Patent

active

055008291

ABSTRACT:
A semiconductor memory device including a memory cell group comprising a plurality of memory cells arranged in a matrix; a specification circuit for specifying a plurality of memory cells addressed by sequential addresses in the memory cells, and for entering them in an active state; a data input/output (I/O) circuit for performing a data read-out/write-in operation (data I/O operation) for the memory cells specified by the specification circuit under a control based on a read-out/write-in signal provided from an external section; a counter circuit for counting the number in response to cycles of a basic clock signal provided from an external section; and a controller for receiving at least one or more specification signals provided from an external section, for outputting a control signal per specification signal for specifying a particular cycle as a starting cycle to count the number of the cycles in response to the basic clock signal, and for instructing the counter circuit to count the number of cycles in response to the basic clock signal based on the control signal, and for controlling a specification operation executed by the specification circuit and the data I/O operation of the data I/O circuit in accordance with the number of cycles in response to the basic clock.

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C. Ohno, "Self-Timed RAM: STRAM"; Fujitsu Sci. Tech. J., 24, 4, pp. 293-300 (Dec. 1988).
Dunn et al., "Single Counter Controlled Buffer", IBM TDB, vol. 20, No. 5, Oct. 1977, pp. 1702-1703.

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