Method and apparatus for mutual exclusion in self-directed distr

Details Method and apparatus for mutual exclusion in self-directed distr Method and apparatus for mutual exclusion in self-directed distr

Filed on

1994-04-14

Date issued

1996-09-03

Examiner

Bowler, Alyssa H.

Other Related Categories

39520019, 3951821, 395726, 395730, G06F 1500

Type

Patent

Status

active

Patent number

055532985

Description

ABSTRACT:
A self-directed distributed system provides a method for mutual exclusion of asynchronously interacting processors. The system comprises a system for control of access to a shared resource in a multi-processing computing environment, comprising at least two processors; an interconnection system interconnecting the processors, whereby each processor can communicate with all other processors; a resource for shared access by the processors; communication means within each processor for sending an interest signal to all other processors for signalling the interest of the processor in acquiring the resource; receiving means within each processor for receiving the interest signal of every other processor; interest vector means within each processor for storing the received interest signal of every other processor; and means within each processor for interrogating the interest vector means in the processor to determine the availability of the resource. Each processor can acquire the resource only if (1) the processor's interrogation of its interest vector means indicates no interest in acquiring the resource by any other processor; For every pair of processors, P1 and P2, the processor P1 delays interrogation of its interest vector means a sufficient time after the processor P1's interest signal is sent, that the time gap between the processor P1's interrogation of its interest vector means and the arrival of the processor P1's interest signal at the processor P2 (T1) is not less than time between the processor P2's interrogation of its interest vector means and the time the processor P2's interest signal arrives at the processor P1 (T2).

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