Output buffer circuits for reducing ground bounce noise

Details Output buffer circuits for reducing ground bounce noise Output buffer circuits for reducing ground bounce noise

1987-08-13

1988-10-11

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307448, 307451, 307475, 307263, H03K 19003

Patent

active

047773898

ABSTRACT:
An output buffer includes a pull-up transistor (N1), a first pull-down transistor (N3), a second pull-down transistor (N8), and a logic circuit (15). The logic circuit (15) is responsive to a data input signal making a high-to-low transition and the output signal making a high-to-low transition for maintaining the second pull-down transistor (N8) turned-off until after an output node has made the high-to-low transition, thereby reducing significantly the ground bounce noise.

REFERENCES:
patent: 4567378 (1986-01-01), Raver
patent: 4622482 (1986-11-01), Ganger
patent: 4638187 (1987-01-01), Boler et al.
patent: 4645952 (1987-02-01), van Tran
patent: 4719369 (1988-01-01), Asano et al.
patent: 4724340 (1988-02-01), Sood
patent: 4725747 (1988-02-01), Stein et al.
patent: 4727266 (1988-02-01), Fujii et al.
patent: 4731553 (1988-03-01), Van Lehn et al.
patent: 4739193 (1988-04-01), Doty, II

Affiliated with

Also associated with

Rating

Output buffer circuits for reducing ground bounce noise does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Output buffer circuits for reducing ground bounce noise, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Output buffer circuits for reducing ground bounce noise will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1959884