Shared bus mediation system for multiprocessor system

Details Shared bus mediation system for multiprocessor system Shared bus mediation system for multiprocessor system

1993-11-01

1996-09-03

Sheikh, Ayaz R.

Boots, shoes, and leggings

395477, 395311, 364DIG1, 364229, 3642292, 364240, 3642407, G06F 1300

Patent

active

055532462

ABSTRACT:
A shared bus control system for multiprocessor system having shared buses for a plurality of processors comprises a bus mediation circuit which outputs the switch control signal to switch accessing to the shared buses by the plurality of processors with synchronizing the system clock and a bus selection circuit which selects the address and data from one processor according to the switch control signal and outputs them to the shared buses. It further comprises a state detection circuit which decodes the bus status signal from the particular processor among the processors and detects the bus state of the particular processor and a clock modulation circuit to modulate the operation clock for the particular processor when the state detection circuit detects the particular bus states.

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