Powerfail durable NVRAM testing

Details Powerfail durable NVRAM testing Powerfail durable NVRAM testing

1995-01-19

1996-09-03

Beausoliel, Jr., Robert W.

Excavating

39518505, 371 211, G06F 1100, G11C 2900

Patent

active

055532381

ABSTRACT:
Powerfail durable non-volatile random access memory (NVRAM) testing is provided by using the available NVRAM itself to remember its own state of testing, by sequencing through the testing process, and by carefully placing memory image checksums within the NVRAM. The correctness of the NVRAM image is maintained while each memory word is tested for functional correctness without additional or specialized hardware. NVRAM is manipulated such that it can detect disrupted testing and restore the NVRAM image as it existed prior to the disruption. Specifically, test variables are kept in the NVRAM itself to retain and manipulate (1) a test-status signal indicative of a status of the memory testing process, (2) data from the memory location being tested, (3) an address for the memory location being tested, and (4) checksums for verifying the accuracy of the data after the memory is tested. These carefully placed control sequences (checksums) allow for detection of numerous hardware corruptions that could potentially occur during the testing process.

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