Patent
1995-03-03
1996-09-03
Beausoliel, Jr., Robert W.
395750, G06F 1134
Patent
active
055532365
ABSTRACT:
A processor (10) has an internal clock circuit (12), a CPU (14), and a test controller (16). The CPU (14) has a low-power mode of operation and a normal mode of operation. When in low power mode, the internal clock circuit isolates the CPU clock (18) from the internal clock (28) and pulls the internal clock (28) to a stable logic state to ensure that the CPU is not changing state and consuming power. The test controller (16) can be in a low power mode along with the CPU (14) or in a normal mode while the CPU (14) is in the low power mode via the test control signal (26). When the CPU is in low power mode and the controller (16) is in normal mode, the controller (16) tests the operation of the circuit (12) to logically ensure that handling of the clock (18) is proper when entering, maintaining and exiting the low power mode of operation.
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Crouch Alfred L.
Revilla Juan G.
Beausoliel, Jr. Robert W.
De'cady Albert
Motorola Inc.
Witek Keith E.
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