Computer system capable of outputting status data without interr

Details Computer system capable of outputting status data without interr Computer system capable of outputting status data without interr

1996-02-07

1999-02-09

Palys, Joseph

39518304, 39518306, G06F 1100

Patent

active

058705414

ABSTRACT:
A computer system such as a debugging system for a microcomputer system includes a display unit and a supervisor for receiving at least one of the plurality of status data from the microcomputer system independently from the execution of a program in the microcomputer system and displaying the read status data on the display unit. The microcomputer system includes the plurality of peripheral circuits respectively having status flags, each of which stores the status data of the corresponding peripheral circuit, and a CPU executing the program. The status data are updated as the execution of the program and the CPU can read the status data of each of the status flags. An emulation control circuit generates a status clock signal independently from the execution of the program by the CPU and a selector sequentially and repeatedly selects one of the plurality of status data in response to the status clock signal to output the selected status data to the supervisor.

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IEEE Journal of Solid-State Circuits, vol. 26, Nov. 1991, pp. 1662-1667.

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