Delay type flip-flop

Details Delay type flip-flop Delay type flip-flop

1979-06-01

1981-07-07

Zazworsky, John

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307291, H03K 3289

Patent

active

042776988

ABSTRACT:
In a master-slave delay type flip-flop, a first transistor transfers the data at the D input to an inverter stage when the clock signal goes low. When the clock signal again goes high, the inverter data is transferred to a second inverter stage which forms the flip-flop Q output. Feedback means have provided for latching the inputs to both the first and second inverter stages. An inverting transistor in one of the feedback paths forms the Q output of the flip-flop. Additional embodiments of the D-type flip-flop circuit include both asynchronous set and reset features.

REFERENCES:
patent: 3812384 (1974-05-01), Skorup

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