Multi-processor system with programmable memory-access priority

Details Multi-processor system with programmable memory-access priority Multi-processor system with programmable memory-access priority

1980-11-21

1983-08-23

Springborn, Harvey E.

Boots, shoes, and leggings

G06F 1516, G06F 1518

Patent

active

044007710

ABSTRACT:
A multi-processor system includes a plurality of processors, a common shared memory, and programmable memory access priority control circuit. The programmable memory access priority control circuits includes a programmable register circuit and a priority control circuit. The programmable register circuit stores priority information designating a memory access grade priority for each of the processors, wherein the priority information is changeable either manually, by external circuit or by at least one of the processors and remains fixed irrespective of access of the memory by any of the processors until being changed. The register circuit outputs priority information signals which indicate the memory access grade priority of each of the processors. The priority control circuit receives the priority information signals from the register means, receives a memory request signal from the processors requesting memory access (i.e. use) of the common shared memory, and outputs an acknowledge signal enabling the processor having the highest memory access grade priority to use the common shared memory in accordance with the priority information.

REFERENCES:
patent: 3676861 (1972-06-01), Ruth
patent: 3696860 (1972-06-01), Collier et al.
patent: 4075691 (1978-02-01), Davis et al.
patent: 4096571 (1978-06-01), Vander Mey
patent: 4096572 (1978-06-01), Namimoto
patent: 4151592 (1979-04-01), Suzuki
Programmable Priority Mechanism, Christensen, IBM TDB vol. 17, No. 7, Dec. 1974.

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