Microprocessor having program counter registers for its coproces

Details Microprocessor having program counter registers for its coproces Microprocessor having program counter registers for its coproces

1990-05-15

1993-06-08

Lee, Thomas C.

Boots, shoes, and leggings

364228, 3642286, 364229, 3642305, 364239, 3642382, 3642318, 3642472, 3642474, 3642477, 3642478, 364243, 364DIG1, G06F 1206, G06F 9302, G06F 1314, G06F 1312

Patent

active

052187110

ABSTRACT:
In a data processing system, the program counter (PC) values of coprocessor (CP) instructions are stored in a queue of a CP, and the stored PC value is not erased until the CP has completed executing the instruction. The need for a queue is caused by the pipeline in the CP. Three instructions may be executing concurrently and an exception may occur for any one of them. Accordingly, at least 3 PC values may be stored in the queue. Early overwriting is prevented by making the queue 4 words deep. Also, the CP must assert a CPST signal before accepting a new command from the micro processor (MC). Thus, if the pipeline is full the PST signal will not be asserted and the MP must wait before storing the new PC value in the queue. Instead of the entire PC, only an entry point is transferred to the CP. When only four PC values are saved, the entry point is only two bits and may be transferred along with the command information in a single bus cycle. If there is more than one CP, a program status word (PSW) includes a CPID for identifying which CP is to execute a received CP instruction. The queue and the PCID system is only used for the first CP. In the event that an exception occurs, the entry point is transferred back to the MP and the PC of the instruction that took the exception is provided.

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"MC 68881/MC 68882 Floating-Point-Co-Processor User's Manual," Motorola, Inc., Prentice Hall, 1987, Section 7.
MC 68040 32-Bit Microprocessor User's Manual May 15, 1989.

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