Software scheduled superscalar computer architecture

Details Software scheduled superscalar computer architecture Software scheduled superscalar computer architecture

1995-04-13

1996-09-24

Swann, Tod R.

Boots, shoes, and leggings

364DIG1, 364DIG2, 3642624, 3642633, 3649462, 3649469, G06F 900, G06F 938

Patent

active

055600280

ABSTRACT:
A computing system is described in which groups of individual instructions are executable in parallel by processing pipelines, and instructions to be executed in parallel by different pipelines are supplied to the pipelines simultaneously. During compilation of the instructions those which can be executed in parallel are identified. The system includes a register for storing an arbitrary number of the instructions to be executed. The instructions to be executed are tagged with pipeline identification tags and group identification tags indicative of the pipeline to which they should be dispatched, and the group of instructions which may be dispatched during the same operation. The pipeline and group identification tags are used to dispatch the appropriate groups of instructions simultaneously to the differing pipelines.

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